The present invention relates to a semiconductor memory device constituted by a synchronous RAM and, more particularly, to a semiconductor memory device which is constituted by a plurality of synchronous RAMs and capable of writing identical data at arbitrary addresses and simultaneously reading a plurality of data.
In general, when data communication is to be performed between remote areas, phase locking between data is required. FIG. 3 illustrates a case wherein data transmission is performed between areas A, B, and C through a synchronous transmission network. In the areas A, B, and C, data transmission is performed with different phases. For this reason, when data is to be transmitted from the area A to the area C via the area B, a phase shift occurs. That is, the phase of the data on the area A side is different from that of the data on the area C side from the viewpoint of the area B.
FIG. 4 shows a case wherein when a phase in the area B is considered as a reference phase, the phase of data a from the area A is shifted from the reference phase by a phase .theta.1, and the phase of data c to the area C is shifted from the reference phase by a phase .theta.2. In this case, there is a phase difference .alpha.=.theta.2-.theta.1 between the data a from the area A and the data c to the area C. For this reason, the positions of pointers indicating the start data, of the respective data a and c, which are indicated by the hatched portions in FIG. 4 differ from each other. Therefore, when the positions of these read two pointers are different from each other, the phase difference .alpha.between the data a and c can be absorbed by correcting the phases of the two data. For this purpose, the data exhibiting the phase .theta.1 may be temporarily written in a memory, and an address corresponding to the phase difference .alpha. may be designated to read the data exhibiting the phase .theta.2 from the memory, thereby correcting the phase difference between the phases .theta.1 and .theta.2.
FIG. 5 shows a conventional semiconductor memory device constituted by synchronous RAMs, which is disclosed in Japanese Paten Laid-Open No. 5-100946. This device is constituted by two two-port RAMs 21 and 22. Data inputs IN of the RAMs 21 and 22 are commonly connected to a data input terminal 16. Second port address inputs P2 of the RAMs 21 and 22 are commonly connected to a write address terminal 18. First and second port clock inputs CLK1 and CLK2 of the RAMs 21 and 22 are commonly connected to a clock input terminal 20. A first port address input P1 of the RAM 21 is connected to a read address terminal 17. A first port address input P1 of the RAM 22 is connected to a read address terminal 19. In addition, a data output OUT of the RAM 21 is connected to a data output terminal 23. A data output OUT of the RAM 22 is connected to a data output terminal 24.
In the semiconductor memory device having the above arrangement, since write address data and write data are commonly supplied to the RAMs 21 and 22, identical data are written at identical addresses of the RAMs 21 and 22. On the other hand, since read addresses are independently supplied to the RAMs 21 and 22, independent data can be read out from the data output terminals 23 and 24. Note that read address data and write address data are always supplied to the RAM 21 at different timings having a difference of, e.g., one time slot, so as to prevent a read address and a write address from coinciding with each other.
In this conventional semiconductor memory device, however, since no limitations are imposed on read address data to the RAM 22, the write address of the data exhibiting the phase .theta.1 coincides with the read address of the data exhibiting the phase .theta.2 when the phase difference between the data a and the data c becomes zero. Such a coincidence of addresses destroys data stored in a two-port RAM on which the limitation that read and write addresses must not coincide with each other within one time slot is imposed.